1. Field of the Invention
The present invention relates to the field of flat panel display screens. More specifically, the present invention relates to the field of flat panel field emission displays (FEDs).
2. Related Art
Cathode ray tube (CRT) displays generally provide the best brightness, highest contrast, best color quality, and largest viewing angle of prior art flat panel displays. CRT displays typically use a layer of phosphor which is deposited on a glass faceplate. These CRT displays generate a raster image by using electron beams which generate high energy electrons that are scanned across the faceplate in a desired pattern. The electrons excite the phosphor to produce visible light which in turn render the desired image. However, CRT displays are large and bulky-Hence, numerous attempts are being made to devise a commercially practical flat panel display that has comparable performance as a CRT display but is more compact in size and weight.
Flat panel field emission displays (FEDs) meet the above requirements and are a potential replacement for CRT displays. An FED device (also called xe2x80x9cthin CRTxe2x80x9d device) is a thin profile, flat display device which renders an image on a flat viewing surface in response to electrons striking a phosphor layer. Within the FED device, electrons are typically emitted by field emission. An FED device typically contains a faceplate (also called frontplate or xe2x80x9canodexe2x80x9d) structure and a backplate (also called baseplate or xe2x80x9ccathodexe2x80x9d) structure connected together through a peripheral or outer wall. The phosphor layer is associated with the faceplate while the electrons are emitted from the backplate. The resulting enclosure is held at a high vacuum.
In the field of FED flat panel display devices, much like conventional CRT displays, a white pixel is composed of a red, a green and a blue color point or xe2x80x9cspot.xe2x80x9d When each color point of the pixel is excited simultaneously, white can be perceived by the viewer at the pixel screen position. To produce different colors at the pixel, the intensity to which the red, green and blue points are driven is altered in well known fashions. The separate red, green and blue data that corresponds to the color intensities of a particular pixel is called the pixel""s color data. Color data is often called gray scale data. The degree to which different colors can be achieved within a pixel is referred to as gray scale resolution. Gray scale resolution is directly related to the amount of different intensities to which each red, green and blue point can be driven.
A typical FED display screen is composed of a matrix of color points where three color points (red, green, blue) make up a pixel. Therefore, an FED display screen contains a matrix of pixels. In one FED display, the color points are individually driven by vertically aligned column lines (to provide a red, a blue and a green color point) and all color points of a pixel are driven by a common row line which energizes an entire horizontally aligned row of color points. An FED display of this type can have 3x number of columns and n number of rows of color points. Because there are three color points per pixel, there are actually x columns and n rows of pixels. Rows are sequentially energized, one at a time, to display a row of information which is presented over all column drivers. Rows are displayed at a very fast rate, one row at a time, until all rows of the screen are displayed to form a frame of information, e.g., until all n*x number of pixels are energized. If a frame is presented at a rate of 30 Hz, the row update rate would be n*30 Hz for a display having n rows.
Video information can be rendered by a display device using interlaced display mode or non-interlaced (xe2x80x9csequentialxe2x80x9d) display mode. In non-interlaced display mode, each of the n rows of a frame are energized at the row update rate, one after the other in numerical sequence from row l to row n, to render a single frame. One such non-interlaced display format is the VGA format that is Popular with personal computers. However, there are many interlaced display modes in use today, such as the interlaced NTSC standard. In an interlaced format, a frame is made up of two fields. The first field displays only the odd rows, skipping the even row. The second field displays the even rows, skipping the odd rows. The field update rate is therefore twice the frame update rate for interlaced displays.
It would be advantageous to provide display circuitry that could render both interlaced and non-interlaced display formats in the same flat panel display device. Such capabilities would enhance the number of viewing formats that the flat panel display device could accept thereby making such a display device more commercially attractive because interlaced and non-interlaced display formats are very popular. It would be further advantageous to provide such a xe2x80x9cdual display mode capablexe2x80x9d flat panel display that also could adjust to the required display format without requiring any manual user involvement thereby appearing transparent to the user.
Accordingly, the present invention provides a mechanism and method for providing display circuitry that is capable of rendering both interlaced and non-interlaced display formats in the same flat panel display device. The present invention further provides such dual display mode capabilities within a flat panel display device where the device also can adjust to the required display format without requiring any manual user involvement thereby appearing transparent to the user. These and other advantages of the present invention not specifically mentioned above will become clear within discussions of the present invention presented herein.
A circuit and method are described herein for rendering both interlaced and non-interlaced video information on a flat panel display apparatus using the same row enable and row driver circuitry for both display modes. Specifically, the present invention allows shift register-type row drivers to be operable to display both interlaced mode or non-interlaced mode video information. The flat panel display apparatus is a field emission display (FED) screen. Within the flat panel FED screen, a matrix of rows and columns is provided and emitters are situated within each row-column intersection. Rows are activated sequentially and separate gray scale information is presented to the columns. In one embodiment, rows are activated sequentially from the top most row down to the bottom row with only one row asserted at a time. When the proper voltage is applied across the cathode and gate of the emitters, they release electrons toward a phosphor spot, e.g., red, green, blue, causing an illumination point. Therefore, each pixel contains one red, one green and one blue phosphor spot.
The present invention includes circuitry for enabling the shift register-type row drivers to operate in one of two different video display modes. In the first display mode, the rows are enabled sequentially with each pulse width being of the sufficient duration (xe2x80x9clong pulsexe2x80x9d) such that the respective row is able to display image data thereon. In this mode, the rows are enabled for the display of non-interlaced (xe2x80x9csequentialxe2x80x9d) video information where each row is sequentially enabled one after the other. A frame of video information therefore comprises n rows for a display having x columns and n rows of pixels. An example of this is the VGA display standard within the field of personal computers. the second display mode, called an interlaced mode, every other row is to be rendered in a first field followed by a second field rendering the other rows. For instance, the first field can display the odd numbered rows followed by a second field displaying the even numbered rows, or vice-versa. Two fields therefore make up the frame in the interlaced mode. An example of this is the NTSC interlaced display standard. Using the same shift register-type row driver circuitry of the non-interlaced mode, the present invention energizes every other row with a row driving pulse too short (xe2x80x9cshort pulsexe2x80x9d) to effect the display of information on the row. In other words, the driving pulse is too short to perceptively energize the row. By alternating pulse widths in this manner, long followed by short, followed by long, etc., an interlaced display mode is allowed wherein every other row is energized but using the non-interlaced row driver/enable circuitry. Interlaced video can therefore be displayed using the same row enable and driver circuitry that otherwise is applicable for non-interlaced display thereby adding flexibility and advanced display capabilities to the flat panel display without requiring two sets of driver circuitry. Moreover, by providing n short pulses, per long pulse, every nth row can be energized for realizing alternate interlaced display modes.
Specifically, embodiments of the present invention include a method of displaying image information on a flat panel display screen having a matrix of pixels aligned by row lines and column lines wherein each pixel is located at an intersection of one row line and several column lines, the method comprising the steps of: a) in synchronization with each energized row, presenting color signals to a plurality of column drivers which respectively drive the column lines; and b) sequentially energizing the row lines wherein only one row line is energized at a time, the step b) comprising the steps of: b1) energizing an ith row line for a sufficient duration which is sufficient to perceptively display image information on the ith row line; b2) energizing an (i+1)th row line for an insufficient duration which is insufficient to perceptively display image information on the (i+1)th row line; and b3) displaying a first field of image information on the flat panel display screen by repeating the steps b1) and b2) for all odd numbered i row lines. Embodiments include the above and wherein the step b) further comprises the step of b4) displaying a second field of image information on the flat panel display screen by repeating the steps b1) and b2) for all even numbered i row lines.
Embodiments also include a field emission display device comprising: a plurality of column drivers each coupled to a respective column line, the column drivers for driving color signals over column lines; a plurality of row drivers each coupled to a respective row line, each row driver for energizing a respective row line when enabled and simultaneously presented with a row-on time pulse; row enable circuitry coupled to the plurality of row drivers for sequentially enabling the plurality of row drivers wherein only one row driver is enabled at a time; and a clock generator coupled to update the row enable circuitry, the clock generator for generating clock pulses which are separated by a sufficient duration to perceptively energize a row line and the clock generator also for generating clock pulses separated by an insufficient duration which fails to perceptively energize a row line, wherein the clock generator is used for the display of non-interlaced video information by generating clock pulses that are separated by the sufficient duration and wherein the clock generator is also used for the display of non-interlaced video information by generating clock pulses separated by the sufficient duration followed by the insufficient duration, in a repetitive manner, to perceptively energize every other row line of the display device.